1. Field of the Invention
The present invention relates to the manufacture of semiconductor structures, and more particularly to the formation of semiconductor regions within a transistor.
2. Description of the Related Art
The formation of high performance transistor structures requires the accurate placement of carefully controlled numbers of dopant atoms in and around the source and drain regions of the transistor. Ion implantation has increasingly replaced gaseous a diffusion methods of doping for a number of reasons, including the ability to implant a carefully controlled amount of dopant into an underlying material to a controlled depth within the underlying material.
In most manufacturing flows, however, subsequent heat treatment steps result in sometimes large amounts of dopant diffusion which alters the location of previously-implanted dopant atoms. Such unwanted diffusion, for example, makes the formation of shallow junction regions in the transistor source and drain regions increasingly difficult.
Arsenic has virtually replaced phosphorus as the n-type dopant of choice for implantation of heavily-doped regions, such as source/drain regions, largely because the heavier arsenic atom diffuses less (for a given heat treatment operation) than the lighter phosphorus atom, and consequently implanted profiles are easier to maintain through subsequent heat treatment operations. For p-type regions, boron is frequently used (for silicon semiconductor devices). The boron atom diffuses more readily than arsenic, and consequently p-type implant profiles are typically more difficult to control. This makes the fabrication of high performance CMOS devices increasingly difficult because the shallow junctions needed for source and drain regions are difficult to maintain through subsequent heat treatment operations.
Moreover, lateral diffusion of dopants from the source/drain regions toward the transistor channel region underlying the gate electrode is also of great concern. As complex doping profiles (such as lightly doped drain (LDD) structures) have become commonplace in high performance semiconductor fabrication, maintaining the spacing between heavily doped source/drain regions and the channel region is increasingly important.